It is desirable that TD-SCDMA systems support GSM as well as the new TD-SCDMA standard. However, there is an inherent incompatibility in the signal timings for the two standards. Conventional GSM systems have an inherent timing which is derived from 13 MHz clock oscillator. In contrast, conventional TD-SCDMA systems have a symbol and chip-rate derived from a 10.24 MHz clock. (From a conceptual point of view, the processing of transmit and receive signals can be done at n-times the chip rate. For simple implementations, usually small values of n are used, of about not greater than 10 (i.e., 2, 4 or 8). Therefore, it is common to require small integer values times the above frequencies).
It is not practical to use a single Phase Locked Loop (PLL) for generating both of the above frequencies, as it would have to operate at a common divisor of the two frequencies, the desired frequency being generated by varying the multiplication factor inside the PLL. However, for the above frequencies, the highest common divisor is only 40 KHz. This requires an extremely large multiplication factor inside the PLL. For example, the frequency multiplication factor from 40 KHz to 10.24 MHz is 256. If a multiple of 10.24 MHz is desired, then the multiplication factor would have to be even higher, for example, 1024 for 4×10.24 MHz. Such high multiplication factors make the output frequency from the PLL very unstable. Moreover, a PLL with such a high multiplication factor is extremely difficult to implement in an integrated circuit due to noise and isolation problems.
An alternative type of clock system is one using digital interpolation. FIGS. 1 and 2 show schematically the principles of a conventional digital interpolator 10, for clock extraction of an input signal 12 having an input clock rate Fi, using circuitry which is clocked at circuit clock frequency Fc different from the desired frequency Fi. The principle of operation is that, although the circuitry operates at the circuit clock frequency Fc, the samples are manipulated numerically or mathematically as if the circuit were operating at a hypothetical clock frequency of Fi. In more detail, the input signal 12 is sampled at the circuit clock frequency Fc by an analog-to-digital converter (ADC) 14, which produces output samples (i.e., ai−1 . . . ai+2) related to the timing Fc. The output from the ADC 14 is fed to a fractional interpolator 16 which re-calculates (interpolates) the samples at timings (b) controlled by a numeric controlled oscillator (NCO) 18. The NCO 18 includes an m-bit accumulator 20 and an m-bit adder 22 which is coupled in a feedback-loop to increment the value in the accumulator 20 by an integer value (i.e., STEP) held in a register 24. The NCO 18 is clocked at the clock frequency Fc, so that the accumulator is repeatedly incremented by the value STEP at the clock rate Fc.
The values 2m and STEP govern the rate and timings of new (interpolated) samples by the fractional interpolator 16, relative to the circuit clock frequency Fc. Each time the adder 22 overflows, an overflow output 26 signals that a “cycle” of the interpolated signal (based on Fi) has been completed, for controlling downstream processing circuitry (not shown). Therefore, the circuit can handle a signal based on a timing of Fi, even though the circuit is being clocked by a different frequency Fc.
However, such an NCO is only capable of generating accurate timings for frequency relationships which can be related by 2m and STEP. The repetition frequency FNCO for the NCO 18 is given by equation 1 as follows:FNCO=Fc×STEP/2m  Eq.(1) 
For the frequencies of 13 MHz and 10.24 MHz (or low multiples thereof) mentioned above for GSM and TD-SCDMA, it is impossible to find values of m and STEP which can satisfy the above relationship. Therefore, it is not possible to use the fractional interpolator 16 and the NCO 18 to generate the desired frequencies accurately. To address this incompatibility, an error responsive control signal 28 can be fed back from the downstream circuitry for varying the value STEP dynamically in response to detected error rates, so that the interpolated frequency approximates the desired input frequency Fi. However, such a circuit inherently has a significant degree of jitter, and relies on an error responsive control signal to dynamically “correct” the incorrect timings from the NCO.
FIG. 3 shows a conventional approach to Quadrature Amplitude Modulation (QAM). The conventional QAM modulator comprises an encoder circuitry 100 which receives data at an input rate (i.e., Fi), and outputs data at a higher output rate (i.e., Fo). Among other circuitry, the encoder circuitry 100 includes a forward error correction (FEC) block 102 which increases the redundancy of N bytes of data to N+R bytes, a symbol mapper 104 which maps, for example, an 8 bit symbol to an n-bit symbol, and a pulse shaper 106 in the form of a k-times oversampling filter. The output bit rate Fo is related to the input bit rate Fi by equation 2 as follows:Fo=Fi*((N+R)/R)*(8/n)*k.  Eq.(2) 
In one implementation for the digital video broadcast (DVB) European Telecommunications Standard (ETS) 300429 (discussed in more detail later), Fo=Fi*(272/47). In order to provide the correct output timing, the encoder circuitry has to be clocked with a clock signal which has a frequency (272/47) times higher than the input rate Fi. Since the value (272/47) is a non-integer value, then using a PLL 108 to generate the clock signal from the input signal requires a high multiplication factor of 272. For the same reasons as those discussed previously, such a multiplication factor results in a high degree of jitter, and makes the PLL 108 very difficult to integrate into an integrated circuit.
In similar manner to that described previously, it is possible to use a conventional NCO to generate the clock signal. However, there are no suitable integer values of STEP and 2m which satisfy the frequency relation of (272/47). Therefore, if a conventional NCO is used, it is necessary to dynamically vary the value of STEP to try to approximate the desired frequency relation.
It would be desirable to provide a more flexible interpolation arrangement using an NCO which provides greater flexibility in enabling different frequencies to be matched without having to vary an increment value dynamically.